The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same and, more particularly, to a technique which is particularly effective when applied to a semiconductor integrated circuit device having an SRAM (Static Random Access Memory).
A memory cell of an SRAM or a semiconductor memory device is composed of: a flip-flop circuit acting as an information storage unit for storing information of 1 bit; and a pair of transfer MISFETs (Metal Insulator Semiconductor Field Effect Transistors) for controlling the electrical connection between writing/reading data lines and the flip-flop circuit.
The flip-flop circuit of the memory cell is composed of a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters, for example. Each of these CMOS inverters is composed of one drive MISFET and one load MISFET. In this case, the memory cell is of a complete CMOS type of a combination of two drive MISFETs, two load MISFETs and two transfer MISFETs. Of these MISFETs, the transfer MISFETs and the drive MISFETs are of n-channel type whereas the load MISFETs are of p-channel type.
A pair of input/output terminals of the flip-flop circuit (the CMOS inverter) are cross-connected through a pair of wiring lines called “local wiring lines”, for example. Moreover, one of these input/output terminals is supplied with a power supply voltage (e.g., 3 V) of a circuit through a power supply voltage line whereas the other is supplied with a reference voltage (e.g., 0 V) of the circuit through a reference voltage line.
In U.S. Pat. No. 5,523,598, issued Jun. 4, 1996, there is disclosed an SRAM of the complete CMOS type, which is equipped with a pair of aforementioned local wiring lines. In this SRAM, the gate electrodes of the six MISFETs constituting the memory cells, the power supply voltage line connected with one input/output terminal of the flip-flop circuit, the reference voltage line connected with the other input/output terminal, the pair of local wiring lines, and the data lines connected with the drain regions of the transfer MISFETs are individually provided in different conductive layers. In this SRAM, moreover, the local wiring lines and other conductive layers (e.g., the reference voltage line) are arranged to intersect each other so that the reduction in the alpha particle soft error resistance, which might occur upon the miniaturization of the memory cell size and the lowering of the operating power supply voltage, is prevented by forming a capacitor element in the intersection region to increase the storage node capacitance of the memory cells.